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8
,. -..
ANALOG DEVICES
CMOS 4Y2 /5Y2 Digit ADCSubsystem
-PRELIMINARY TECHNICAL DATA FEATURES Resolution: :1:41/2 Digits BCD or f20k Count Binary Capability for 5 1/2 Digit Resolution or Custom Data Formats Data Format: Multiplexed BCD (for Display) and Serial Count (for External Linearization, Data Reformatting, or Microprocessor Interface) Accuracy: :1:1Count in :l:20k Counts Scale Factor Drift: 0.2ppmfC- Using Only MediumPrecision Op Amps Requires only a Single Positive Reference Overrange Display Auto Calibration Capability Interfaces to TTL or 5V CMOS HOLD Input and SCC (System Conversion Complete) Output for Interface Flexibility ."
OBS
8
~
VREF>
GENERAL DESCRIPTION The AD7555 is a 4 1/2 digit, monolithic CMOS, quad slope integrating ADC subsystem designed for display or microprocessor interface applications. Use of the high resolution enable input expands the display form~t to 5 1/2 digits BCD. With SCO (Serial Count Out) connected to SCI (Serial Count In), the output data format is multiplexed BCD suitable for visual display purposes. As an added featUre, SCO can also be used with rate multipliers for linearization, or with BCD or binary counters for data reformatting (up to 200k binary counts). The quad slope conversion algorithm (Analog Devices patent No. 3872466) converts the external amplifier's input drift errors to a digital number and subsequently reduces the total system drift error to a second order effect. Using only inexpensive, medium-precision amplifiers a scale factor drift of o.2ppmf C is achieved. PIN CONFIGURATION
f1l
OLE
VREF> ( 1
AD7555 FUNCTIONAL DIAGRAM
TE
Do ,
,B8 B4, B2
BCD DATA
.
AD7555
TOP VIEW
, os
DATA
.
STROBE
BJ ,
ORDERING -Model AD7555BD -- ,- -AD7555KN
INFORMA nON
T 0
i
.
peratmg
Range
" ~~-
Package
I Temperature
28 Pin Side Brazed Ceramic -25C to +85C -.j --28 Pin Molded Plastic 0 to +70oC
--
~
151 $C1
8
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Route 1 Industrial Park; P.O. Box 280; Norwood, Mass. 02062 Tel: 617/329-4700 1WX: 710/394-6577 West Coast Mid-West Texas 714/842-1717 312/894-3300 214/231-5094
SPECIFICATIONS +5V, Vss = -5V, VREFl (Vcc=
LIMIT AT PARAMETER
ANALOG SWITCHES RON (Switch 1-3) L'lRON (Switch I) versus AlN Mismatch Between Any Two Switches (excluding SWO) lLKG (Switch OFF) SWO (pin 6) SWI (pin 2) SW2 (pin 3) SW3 (pin 1) (BUFIN, 800 300 300 1 1 1 1 3 3.0 0.8 1 1200 500 500 70 70 70 70 200 3.0 0.8 10 3.5 0.8 3.0 0.8 1.5 -1.5 300 -150 TA LIMIT AT TA
= +4.0960V, FCLK = 614.4kHz, AGND = OV) UNITS
f2 max f2 typ f2 typ nA max nA typ nA typ nA typ nA Vmin Vmax j1A max Vmin Vmax Vmin Vmax mA max mAmax j1A max j1A max
= +2SoC
= Tmin' Tmax
CONDITIONS/COMMENTS
-2VAlN+2V -2VAlN+2V -2VAlN+2V IRJCT (pin 5) =+2.048V OVlROUT (pin S)+10V AIN =+2V to -2V, BUFlN = OV and +4.096V AGND = OV, BUFIN = -2V to +2V, +4.096V VREFl = +4.096V, BUFIN = -2V to +2V 1 of SW1, 2, 3 on Refer to Functional Diagram
8
4)
OBS
CLOCK INPUTS (pin 12 and 13) VINH (CLK) VINL (CLK) VINH (DMC) VINL (DMC) IINH (CLK) IINL (CLK) IINH (DMC) IINL (DMC) 3.5 0.8 3.0 0.8 1.0 -1.0 200 -100 DIGITAL OUTPUTS DO - OS (pins 22-27) VOH VOL VOL B1, B2, B4, B8, DAV, SCC, SCO (pins 20,19,18,17,10,11,16) VOH VOL DYNAMIC PERFORMANCE DMC Pulse Width DMC Frequency CLK Frequency Propagation Delay DMC HIGH to DA V HIGH DMC HIGH to DA V LOW DMC HIGH to BCD Data on B8,B4, B2, Bl DMC LOW to Digit Strobe (DO -OS) LOW POWER SUPPLY ICC lss VCC Range VSS Range Specifications subject to change without notice. 5 5 +Sw+17 -5 to -17 4.5 4.0 0.5 4.0 0.5 5 100 1.5 5 5 5 5
CONTROL INPUTS (pins 7, 8, 9,15) VINH VINL IINH or IINL
VIN
= OV
or VCC
OLE
4.5 4.0 0.8 Vmin Vmax Vmax ISOURCE
ISINK
= 40j1A
= SmA
(Display
ISINK= 1.6mA (TTL Load)
4.0 0.8 5 100 1.5 7 7 5 5 5 5 +Sto+17 -Sto-17
Vmin Vmax j1s mm kHz max MHz max j1s max j1s max j1s max .. /ls max mA max mA max V V
ISOURCE =40j1A ISINK = 1.6mA
TE
Driver Load)
8
See Figure 3 Typical fOMC is 1.SkHz with COMC = O.Olj1F
See Figure 3
Dunng Conversion During ConversIOn See Absolute Maximum
Ratings
8
-2-
ABSOLUTE MAXIMUM RATINGS
8
VeetoDGND VsstoDGND VeetOVss DigitaIOutputs Digital Inputs
DMC (Pin 13), CLK (Pin 12)
+17V 17V +22V Vee,DGND
Power Dissipation (package) Plastic (AD7555KN) To+50C
1200mW
. . . . . . . . . . . . . . Vss, Vee
Derate above +50C by. . . . . . . . . . . . . . . . 12mW/C Ceramic (AD7555BD) To+50C 1000mW Derate above +50C by. . . . . . . . . . . . . . . . 10mW/C
*Whichever tWhichever is the least positive. is the least negative.
OBS
AD7555BD (Ceramic)
All other Logic Inputs. . . . . . . . . . . . . . . DGND, +17V Analog Inputs/Outputs AGND to DGND (Positive Limitation) . . . . Vee or VlROUT* AGND to DGND (Negative Limitation).VSs or VIROUT-20Vt AIN (Pin 2), VREFI (Pin 1), BUFIN(Pin4) Vee,VSS IRjCT (Pin 6), IROUT (Pin 5). . . . . . . . +27V, AGND Operating Temperature Range AD7555KN (Plastic) . . . . . . . . . . . . . . . . . . 0 to +70C
. . . . . . . . . . . . . .-25Cto
+85C
NOTE: Do not apply voltages to any AD7555 digital output, AIN or VREFI before Vee and Vss are applied. Additionally, the voltages at AIN, VREFI or any digital output must never exceed Vee and Vss (if an op amp output is used to drive AIN it must be powered by the AD7555 Vee and Vss supply voltages). Do not allow any digital input to swing below DGND.
StOrageTemperature. . . . . . . . . . . . . . . . -65C
to +1500C
Lead Temperature (Soldering, 10s). . . . . . . . . . . . . +300C
CAUTION: ESD (Electro - Static - Discharge) sensitive device. The digital control inputs are zener protected; however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The foam should be discharged to the destination socket before devices' are removed. SYSTEM ELECTRICAL CHARACTERISTICS (TA =0 to +45C) Characteristics refer to the system of Figures 6a and 6b. Vee = +5V, VSS = -5V, VREFI = +4.096V, error count n calibrated to zero at TA =+25C as per procedure on page 9 unless otherwise noted. Switch leakages and limitations in temperature performance of auxiliary components (such as the integrating capacitor) cause performance degradations above +45 C CHARACTERISTIC Resolu tion LIMIT 4 1/2 Digit BCD 5 1/2 Digit BCD :tl Count max :tl0 Count max
:tl/2 Count max :t2 Counts max 610ms max 1,760ms NOTES: '41/2 digit mode; max
8
OLE
CONDITIONS/COMMENTS :t20,000 Counts :t200,000 Counts (See Note 1) 41/2 Digit BCD 5 1/2 Digit BCD (See Notes 1 and 2) 4 1/2 Digit BCD 5 1/2 Digit BCD (See Note 1) 4 1/2 Digit BCD 5 1/2 Digit BCD (See Note 1)
TE
Relative Accuracy
Count Uncertainty Due to Noise (Flicker)
Conversion Time
feLK = 614.4kHz, HREN = LOW, Rl = 360kn el = O.22;LF 5 1/2 digit mode; feLK = 1.024MHz, HREN HIGH, l = 750kn = R el = O.22;LF 2Assumes voltage reference (VREFl) Te of Oppmfe.
-I ,
I
L-
-3-
Applying AD7555 the
AD7555 ANALOG VREFl AIN AGND BUFIN IROUT IRjCT
I~"""""""';"
LOGIC OUTPUTS B8 - B1 (Pins 17 20)
D5 BCD8 - BCD1 output, (Sce table 1) Active HIGH
PIN DESCRIPTION FUNCTIONS (Pin (Pin (Pin (Pin (Pin (Pin
oo..oo-.
1): 2): 3): 4): 5): 6):
(LOGle INPUT~S.
. COMP' (Pin 7): (Pin 8): HREN
+4.096V Reference Inpur Analog Input Voltage (:t2V Full Scale) Analog Signal Common Ground To External Buffer Amplifier Input From Integrator Amplifier Output To Integrator Amplifier Summing junction .. .. Input from the external comparator. High Resolution Enable, determines converter resolution HREN
(Pin 22):
.-
10-5 digit output, Active LOW in 5 1/2 digit mode, stays HIGH in 4 1/2 digit mode 10-4 - 10-1 digit outputs, Active LOW 10 /overflow/polarity Active LOW output,
8
04 - D 1 (Pins 2327) .DO (Pin 27): SCC (Pin 11):
= LOGIC LOW, Full Scale = :t1.9999V (1001lV resolution)
System conversion complete, goes HIGH when conversion is complete, returns LOW on comparator crossing at end of phase 0 integration period. Serial Count Out, a serial output pulse train proportional in length to the magnitude of AIN. SCO can b~ externally pulled HIGH while DA V = HIGH to display the error count "n" for calibration purposes (see page 9).
SCO
(Pin 16):
OBS
HOLD (Pin 9): HOLD
HREN = LOGIC HIGH, Full Scale = :t1.99999V (lIlV resolution)
Hold Input HOLD = LOGIC HIGH, the ADC converts and updates the displays continuously as per the timing diagram of Figure 3.
=LOGIC
LOW, the ADC is
reset and conversion is disabled. Data; from the last complete conversion con1 tinues to be displayed. To ensure most! recent data is displayed, HOLD should!
be taken LOW when DAVis
not
HIGH. When HOLD returns
the next leading edge of DMC initiates a new conversIOn.
DMC (Pin 13): Display Multiplexer Clock, can be driven from an external logic source,' or with the addition of an external
OLE
DAV i(Pin 10):
!
.
HIGH,
Data Valid - When low, DAV indicates that the data being presented on the BCD output bus is valid. DAV goes high on the first positive edge of DMC after a conversion is complete and returns low two DMC pulses later. When it returns low, the digit counter is reset to DO. This is termed the MASTER RESET.
capacitor, will self oscillate. With an external capacitor of 10,OOOpF, DMC oscillates at approximately 1.5kHz at ~ 5% to 10% duty cycle, suitable for display purposes. CLK (Pin 12): Clock Input for maximum line rejec~ tion in the 41/2 digit mode; 50Hz: fCLK =512kHz (= 4.096MHz
';-8)
TE
LED DISPLAY WHEN USING 7447 SEGMENT DECODER
8
DATA
B8
B4 B2 B1
0
0 0 0 0
0 0 0 0 1 1 1 1 0 0 1
0 0 1 1 0 0 1 1 0 0 0 0 1 0
0 1 0 1 0 1 0 1 0 1 0 0 0 0
,-, '...I
C
.
4
0 0
(..1
,
60Hz:
fCLK
= 614.4kHz
(= 4.915MHz
=,
0
1 I I
';-8) SO/60Hz: fCLK =409.6kHz (= 3 .2768MHz.;- 8) For maximum line rejection 5 1/2 digit mode; SO/60Hz, fcLK = 1.024MHz (=4.096MHz.;-4) SCI (Pin 15): in the
6
0 0
8 9
'-. =..
,_,
" " -, .
t:
OVERFLOW
+1 DI~IT ONLY -1 + 0 0 1 0
0 0 1
Serial Count In. Input to totalizing counter in the A07555. SCI is normally connected to SCO for direct count totalization.
{
.
.
SUPPLY Vcc VSS DGND
INPUTS (Pin 28): (Pin 14): (Pin 21):
Tab/e 1. Output Coding Positive Supply Input (+5V) Negative Supply Input (-5V) Digital Ground
8
-4----
8
Component limitations such as switch leakage, as well as operational amplifier offset voltage and bias current (and the temperatUre dependency of these errors), are major obstacles when designing high resolution integrating AID converters. The AD7555 however, utilizes a patented quad slope conversion technique (Analog Devices Patent No. 3872466) to reduce the effects of such errors to second order effects. Figure 1 shows a simplified quad slope integrator circuit. The various inputs AGND (Analog Ground), VREFb and AIN (Analog Input) are applied in sequence to the integrator via switches 1-3 (see Table 2), creating four slopes at the integrator output (phase 1-4 of Figure 2). If the equivalent summing junction voltage Vs is precisely O.5VREFl, the phase 1 and phase 2 integration times are equal, indicating there are no input errors. If Vs =1=.5VREFl (due to amplifier offset 0 voltage, bias current, etc.), an error count "n" is obtained. The analog input integration cycle (phase 3) is subsequently lengthened or shortened by "n" counts, depending on whether the error was positive or negative.
SWO
N(AIN;;'O)~KT
'
[ v---' ] . [
VREFI +KT
A1N
.
A1N
VREF1I
][ .r--a
2
AGND
+ VREFI (1 + 2a)
]
2
'
IDEAL TERM
ERROR 1 FRM
EQNl
N
(AIN <0)--
.
-
K
'
T
[ A1N ]' .K [
VREFI T
AIN
VREFI -
1
][
--a2
AGND (1
+ VREFI +
)
a
]
IDEAL TERM
ERROR TERM
EQN2
WHERE:
N
= Number
of counts
appearing
at AD75 5 5 Serial
Count Out pin corresponding to the analog input voltage, AIN. AIN = Analog Input Voltage to be digitized KT
OBS
VREF2
Vs 0 VRE'2 + Vos + IBIAS R, + IlKGSWO R,
=40960
counts (4 1/2 Digit Mode) 409600 counts (5 1/2 Digit Mode)
AGND
48
Figure 1. Simplified Quad Slope Integrator Circuit
PHASE 4 PHASE 0 PHASE -1-1 1 PHASE 2
OLE
VREF2 VOSl
at AD7555 pin 3 (AGND) measured with respect to VREFl and AIN signal common ground. (Ideally, AGND = OV) . 2VS - VREFl a ISan error term equal to VREFl Ideally a = 0 when Vs = 0.5VREFl' NOTE: Vs = VREF2 + YOSt + VOS2+ IB2Rl + IswoRl WHERE:
= Voltage
= 0.5VREFl if = Offset voltage
buffer the effect of .0,RONof SW1 - SW2) VOS2 = Offset voltage of integrator amplifier A2 IB2Rl
.
PHASE 3
~ lAIN = +FSI I 4 PHASE
= Equivalent
~
-lAIN
I
1
integrator amplifier offset voltage due to bias current of A2 integrator amplifier offset voltage due
to SWO leakage current.
0
PHdsE 4 lAIN -FSI0
01-1
IswoRI
=Equivalent
TE
no error is present of buffer amplifier Integration toO=RICI tOI = KIt t02 = (Kl + n)!
Al (required
to
If AGND = 0, then the error terms of EQN 1 and 2 contain
~-?-/
/
"" I \','i'
,JI",l "I
I
,I'"'
,"
'-..'-..
'-.. '-..
1
I I,-
J>.~"'--"'-:---" "" " """
only second order effects due to a =1= . Thus, the AD7555 O is a powerful tool which allows high precision system performance to be obtained when using only moderate precision op amps. "Other advantages of the quad slope technique include bipolar operation using a single positive voltage reference, and the fact that since the comparator propagation delay is constant hysteresis effects are eliminated. (This is because the comparator always approaches the zero crossing from the same direction). Switch Closed Phase 0 1 2 3 4 5 (Figure SW3 SW2 SW3 SW1 SW3 SWO 1) Equivalent Input Voltage VREFI - Vs AGND - Vs VREFI - Vs AIN - Vs VREFI - Vs RESET
j
-too
R,C,
=
I
4K, t
I
Klt
,
.
1
4K,t
'01=__t02=-l=t03=12Kl-nltK" IK,+nlt
l
-to4=
12K,+n-Nlt
M
Nt~
Nt~
l-t04=12K, +n+Nlt NOTES' ,. FOR 4 1/2 DIGIT MODE, K, = 10.240 t = 4 X 1!IClK, WHERE fCLK IS CLOCK FREOUENCY AT PIN 12 2. FOR 5 1/2 DIGIT MODE, K, = 102.400 t = 2/ICLK, WHERE ICLK IS CLOCK FREQUENCY AT PIN 12 3. n = ERROR COUNT DUE TO AMPLIFIER OFFSETS ETC. AND CAN BE POSITIVE OR NEGATIVE.
Time
Figure 2. Quad Slope Integrator Output
8
The final effect is to reduce the analog input error terms to second order effects. This can be proven by solving the differential equations obtained during the phase 1 through phase 4 integration periods. Barring third (and higher) order effects, the solutions are given in equations 1 and 2.
t03 t04
=(2K 1 - n)! =(2Kl + n:!:N)!
INTEGRATOR
Table 2. Integrator Equivalent Input Voltages and Integration Times
-5-
TIMING AND CONTROL Figure 3 shows the AD7555 timing. SCC goes HIGH at the end of SCO indicating conversion is complete. DA V goes HIGH on the 1st leading edge of DMC after conversion is complete. New data is strobed into the data latches (see functional diagram) on the leading edge of the 2nd DMc. DA V returns low on the leading edge of the 3rd DMc. BCD data is placed on B1, B2, B4, B8 on the positive edge of DMC while the digit counter is incremented on the negative edges of DMC. A reset phase (phase 0) is initiated on the 4th DMC after conversion is complete. SCC returns low at the phase 0 comparator crossing indicating a conversion start. If the DMC oscillator is set up to free run (C8 in Figure 6b causes DMC to run at about 1.5kHz), the AD7555 will continuously convert and update the displays.
oMC seo
5a and 5b show the recommended P.c. board layout for the AD7555. Figure 4 shows the component overlay for Figure 5a.
oAV ht OMe AFTER see
UPDATE DATA LATCHES TO NEW DATA (2nd oMC AFTER See) PHASE 0 STARTS ON 4th oMC AFTER sec PHASE 0 COMPARATOR CROSSING (SCC IRETURNS LOW)
--.nnmL
NEGATIVEAIN
POSITIVE AIN
PHASE 0
t ~"AS'
see
LJI
oAV
j
OBS
played as ft. '-'1..'L'!..Jand a negative overflow .as when using the 7447 seven-segment decoder.PRINTED CIRCUIT LAYOUT with the system
Rl-14200 DS6 DLlOl AL TERNATIVE
Externally controlling a means of controlling applications. Pages 10 to interface the AD75
the generation of DMC pulses provides data outputting for computer interface and 11 illustrate how to use this featUre 55 to a microprocessor.
~
DO=-=-=======~~
I;
I'
.I
DATA NOT VALID
m~~~
=~
---I
~'
~I
~
DISPLA Y The output data format of the AD7555 is multiplexed BCD as per the Timing Diagram of Figure 3. The output code format is shown in Table 1. Overflow causes digit 1 through digit 4 (digit 1 through digit 5 in 5 1/2 digit mode) to output a BCD 12 (1100). Overflow does not affect digit O.Therefore, a positive overflow is dis-
/.
To ensure performance
specifications
OLE
~
02 u
-------.---
_u-
~ 1 OJ =~~~=~-=--=-]
04=
=-=
=]
lJ5 -~
I
U
LI ,_, '-,
gCD~A~;;08
=ITb
A , I-OATNOT
-DLoDATA
+
00 NEW oATA-
Figure 3. Timing Diagram (Self Start DPM Mode)
Figures
SIZE CRYSTAL C6 3P F C4
200
R5
[U
R
~
DS5 DLlOl
'4
f--W~R~~:R~~1
[!]
I'F1rr1 ~
~
:
,'1./ I
I
x,
:
I
I
I
01 4.7V-#-
(29~G G{ ~
3 3
TE
~
VALID
02
~ ,~--r
~
~
1
0
0 0
AD30'
A2
A'..-
R'5
10k
C3
R1750k
R7 , A A Gl, ih
rL- I
-~ r~
:rO""':I C1
",,' oii"r
R4 10k
~(jj)
R6 10k
~
DS4 DLl07
~
]h
~ ~
R9
~~
R13
Rl0:
74C901
<51)0.01"F
C8
0.01;~ c:.> ~
DS3 DL70l
~ ~R12n
""""""
I
".
A~\
:1 555
DS2 DLlOl
~
~
~~ ~
~71~9~~
j
(
DS1 DLl01
~
04
~R11
~ ~",~",w
"",,'",
2N3l02
~02~
L>'i<:~ 9
06
~
R34lk
+CJ,~:F
? ?c~?
05
20 3 40 5 60 7 80 9 10 0 11 12 0 13 14 0 15 160 17 18 0 19 20 0 21 22 0 23 24 0 25 26 0 27 28 0 29 30 0 31 32 0 33 34 0 35 36 0 37
Vss Voo AIN AGND DAV EXT DMC
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAV VREF1 CAL HREN HOLD seo 88 81 84 82 DGND Vee
01-062N3l02
Figure 4. Component Overlay for Figure 5a
-6~--
8
PCB Layout is reproduced on a one to one scale. Note that a pad already exists on the PCB layout for an AD584LH voltage reference, suitable for 4 1/2 digit operation.
- .. 3
1
OBS
8
13 . 14. 15 . 16. 17. 1S. 19 . 20 .
10. 11. 12.
s. 9.
6 7-.
OLE
Figure 5a. Component Side
23. 24 . 25. 26.
if.
21. 22.
TE
18
Figure 5b. Foil Side
-7-
ANALOG CIRCUIT SET-UP AND OPERATION The following steps, in conjunction with the analog circuitry of Figure 6a explain the selection of the various component values required for proper operation. 1. Selection of Integrator Components Rl and Cl Improper selection of the integrator time constant (time constant = R 1Cl) may cause excessive noise due to the integrator output level being too low, or may cause nonlinear operation if the integrator output attempts to exceed the rated output voltage of the amplifier. The integrator time constant Rl Cl must be:
(VREFI )(Ka) (fCLK) (7V) ~Rl Cl~ (VREFl)(Ka) (fCLK)(VDD -5V)
nected to the output of the integrating amplifier, not to its summing junction. The recommended maximum value for Rl in both the 4 1/2 digit and 5 1/2 digit mode is 750kSl. Higher values may.cause noise injection. 2. Determing Conversion Time Maximum conversion time occurs when AIN = -FS and is given by 4 1/2 DIGIT MODE tCONVERT= (325,760)(tcLK) 5 1/2 DIGIT MODE
tCONVERT
8
+ Rl Cl
+ Rl Cl
= (l,628,800)(tCLK)
Where: VDD is the integrator amplifier positive supply voltage fCLK is the clock frequency at pin 12 Ka = 8.2 X 104 (4 1/2 digit mode) or 4.0 X 10s (5 1/2 digit mode)
Where: tCLK = Period of CLK as measured at pin 12 Rl Cl = Integrator Time Constant 3. Initial Calibration a. Adjust VREFI so that the voltage at pin 1 (VREFl) of the AD7555 is +4.0960V. b. Apply OV to AIN and adjust R5 (VREF2 Adjust) for display 0.0000. (See optional calibration procedure on the next page for more precise calibration.)
OBS
AGND-OGND
The integrating capacitor must be a low leakage, low dielectric absorption type such as teflon (5 1/2 digit mode), polystyrene or polypropylene (41/2 digit mode). To minimize noise injection, the outside foil of Cl must be con-
INTERTIE
+2VTOO2VI AIN AIN RETURN
~
RETURN
OLE
Voo
{ 0----
VOO. Vss SUPPLY
TE
= +15V
t
VREF1 NOTE
r~ i
3 l,VREF1 RETURN
R420k NOTE2 R5 200 R610k NOTE 2
Rl 75Ok NOTE I I 2
Cl0.24NOTE 2 R15 10k
NOTES, ,. R,C, VALUES SHOWN ARE FOR 51/2 DIGIT MODE. FOR 41/2 DIGIT MODE R, = 360k. C, = 0.24Vss' -5V
Figure 6a. Analog Circuit Diagram APPLICA nON HINTS 1. See Note under Absolute Maximum Ratings for proper power sequencing and input/output voltage ratings. 2. For linear operation the absolute magnitude of AIN cannot exceed 1/2 VREFI. In no case must AIN be more negative than Vss. 3. Do not leave unused CMOS inputs floating. 4. Check that integrator components Rl and Cl are chosen as per paragraph 1 of the setUp and operation section on this page and that initial calibration as per paragraph 3 has been
accomplished. A resistor value no larger than 750k is reccommended to minimize noise pickup. 5. For optimum normal mode noise rejection, use the crystal frequencies shown on page4. 6. In order for the calibrate mode (on the next page) to display the error count properly it can be shown that VREF2~VREFl X 0.4883 Specifically, for VREFI = 4.0960V VREFl~2V 4
-8-
8
LOGIC AND DISPLAY CIRCUITRY The AD7555 possesses 41/2 digit accuracy with potential for 5 1/2 digit resolution. Figure 6b shows the logic and display circuitry when operating the AD7555 with this high resolution.
MODIFYING THE FULL SCALE DISPLAY Availability of the SCO and SCI terminals on the AD7555 provides flexibility for range-switching and modified dataformat applications. For example, in the 5 1/2 digit mode, inserting a + 5 counter between SCO and SCI provides a full scale count at SCI of 39,999 counts (199,999+5).
VCC'
+5V
OBS
8
NOTES. FOR 4112 DIGIT MODE HREN IPIN FOR 5 1/2 DIGIT MODE HREN (PIN 2. SEE ClK PIN DESCRIPTION (PAGE REJECTION INFORMATION. 3.06 AND DSO ARE NOT REOUIRED OPERATION. 4. CALIBRATION CIRCUITRY SHOWN , 81 = lOGIC LOW 81 = lOGIC HIGH. 4) FOR LINE FOR 4 1/2 DIGIT IN FIGURE 7.
I
+5V SUPPLY DGND RETURN
AD7555 IC'
OLE
VCC = +5V
VCC = +5V
'2
R7 W'o R8
'"
R9
11
NOTE 4
IC2 10 9
RIO R11 R12 R13
7447
15 14
8
TO DGND
R7-R13 200" I
Vss
-5V
NOTE 4
fOLK = '.O24MH,
02 IN914
TE
11
sec
TO +15V
Figure 6b. Logic and Display Circuitry (for 5 1/2 Digit Resolution) CALIBRATING THE AD7555 When the AD7555 is placed in the calibrate mode, any resulting error voltage in Vs (summing junction voltage), due to drift, etc., will be contained in the resulting display. To display the error SC1 and seo must be taken HIGH (only allowable when DAVis HIGH). In the calibrate mode the display indicates +16.0480::!:n (+16.04800 ::!:n 5 1/2 digit in mode) where 16indicates a blanked digit and n is a number represen ting the reference inpu t errors. This gives the change required in VREF2 (::!:1:1VREF2) proper calibration (ie., for
n "" 0). The exact relationship be shown to be equal to: (VREFl )n 1:1VREF2 = 40,960 + n between nand 1:1VREF2 can
Figure 7 shows the hardware connections for manual calibration. With the switch in the calibrate mode, adjust VREF2 (potentiometer R5 as shown in Figure 6a) until the display reads +16.0480(+160.04800 in 5 1/2 digit mode). The AD7555 is now calibrated to the center of its error correcting range. Return the switch to normal to resume normal conversion.
+5V
I 'NORM I R3
CAL
+5V
AD7555
SCO sct
,3 DAV
DAV AIN
AIN
(4 1/2 digit operation)
DAV AIN
8
1:1 REF2 V For this capability
= 40,960 + IOn
to operate,
(VREF1) IOn (5 1/2 digit operation) IVREF21 must be 1/2 VREFl ::!:2%. Figure 7. Hardware Requirements Calibration of n = 0
: LI
CAl
VRm
for Manual
-9--
Microprocessor Interfacing
AD7555 AS A POLLED INPUT DEVICE (MCS-85 SYSTEM) Figure 8 shows an AD7555/8085 interface. The DMC clock inpu t of the AD75 55 is controlled by the microcompu ter via an output port of the 8155. Typical timing for this interface mode is shown in Figure 9. D-A goes HIGH on the 1st DMC leading edge after SCC goes V HIGH. It returns LOW on the rising edge of the 3rd DMC pulse. Digit zero is availabe on B1, B2, B4 and B8 at this time. The leading edge of the 4th DMC pulse initiates a new conversion and places digit 1 on B1, B2, B4 and B8. Table 3 shows a procedure for polling the AD7555.
AD7555 AS AN INTERRUPTING INPUT DEVICE (MCS-85 SYSTEM) The AD7555 DMC oscillator provides DMC pulses until SCC (System Conversion Complete) goes high. This causes an interrupt on the RST 7.5 line whereby the three-state buffer is activated and the microprocessor takes control of DMc. Table 4 shows a procedure for using the AD7555 in this mode. Figure 10 shows the basic hookup.
8155
SCC
TO 8085 RST7.5
OBS
8155
AD7555 SYSTEM AS PER FIGURE 6a AND 6b
PDRTCI~ 1/474126 THREE.STATE BUFFER
\l TO DGND
I
f:itfJ'~g~bl
DMC
PORT C
Figure 8. AD7555 as a Polled Input Device
PHASE 4 COMPARATOR CROSSING PHASE 0 START
IROUT
pI;4SE.
POLLED DMC FROM 8155
OLE
Interrupt Enable Three-State Put DMC HIGH DAV HIGH' Put DMC LOW
Figure 10. AD7555 as an Interrupting Input Device (MCS-85 System)
Entry (SCC Goes High Causing Interrupt) Buffer (74126 as Shown in Figure 10)
~~~
Put DMC LOW Put DMC HIGH DA V LOW'
3L-J4L-J5L-J6L.J7
SCC DAV
--J
~
~
IIIII
I
j I L-
P/~o
Put DMC LOW
-
I
I
I
BCD DATA TO 8155
I
I
III
Read BCD Data (Digit 0) Put DMC HIGH Put DMC LOW
TE
PREVIO~
04
Read BCD: Data (Digit 1) etc. Read BCD Data (Digit 4) Disable Three-State Buffer Return to Mam Program
Figure 9. Timing Diagram for Operation as a Polled Input Device (80851AD7555)
Put DMC IIIGII DAV IIIGII?
--.
!ll
Put DMC LOW Delay or Main Program
Vs
Put DMC LOW PutDMClliGIl Put DMC LOW Put DMC IIIGII Put DMC LOW
.
I
Table 4. Procedure for Interfacing the AD7555 as an Interrupting Input Device
Read BCD Data (Digit 0) Put D.\\C IIIGIl (Initiates New ConverSIon) Put D,\\C LOW Rcad BCD Data (Digit I) Put DMC IIIGIl Put DMC LOW
",," 'TO<'
,""""
Rcad BCD Data (Digit 4)
J
-10-
Table 3. Procedure for Interfacing the AD7555as a Polled Input Device
0
OPTO-ISOLATED SERIAL INTERFACE Figure 11 shows a serial interface to the MCS-85 system. This system can accommodate a remote interface where a commonmode voltage is expected to exist between system grounds. Thc 8155 counterltimer is only 14 bits long, i.e., it can only count down from Z14; therefore sca output from the AD7555 (ZOk counts full scale) has to be divided by 2 with consequent reduction in system resolution. Port C of the 8155 is configured as a control port. Port B is an input port. This port configuration is necessary if sign information is required. Magnitude information is obtained by
interrogating the 8155 counter value. The rising edge of DAV is used to cause an interrupt on the RST 7.5 line. The value (Z14 - I~ I) in the 8155 counter should now be read. When DAV returns low the 8155 counter is reset to FFH' Sign information is checked at this time since Do BCD data is present and stable on the BCD bus (see Figure 9). The B2 line of the BCD bus is latched into port B by the signal on B STB i.e. the falling edge of DAV. This causes a rising edge signal on BF (buffer full) to call the 8085 CPU to read the B2 bit. B2 bit is HIGH for negative data, LOW for positive data.
OBS
AD7555 ANALOG SYSTEM PER FIGURE 6a
ISOLATED
AD7555
POWER
SYSTEM
MCS-85
POWER
SYSTEM
B2
AIN
ANALOG INPUT
8
NOTE: SYSTEM RESOLUTION CAN BE INCREASED BY PROVIDING SUFFICIENT COUNTER CAPACITY TO TOTALIZE 20k (OR 200k) COUNTS.
OLE
-=-} +5V OPTO ISOLATOR
"';-2 +5V RETURN
PORT B
(
TIMER! COUNTER SECTION
10,000 COUNTS FULL SCALE
+15V, -5V RETURN
TE
Figure 11. Optically Isolated Serial AD7555/MCS-85
Interface (Full Scale = 10,000 Counts)
.
-11-
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-PIN CERAMIC DIP (SUFFIX
D)
8
a ex)
0.06 (3.05)
~
0.12 (1.53)
1 m
I
~
,... It) U
OBS
0.065 (1.66)
.I. ...!
0.095 (2.42) 0.045 (1.15) NOTES, LEADNO. 11S IDENTIFIED8Y DOTOR NOTCH. LEADSARE SOLDEROR TIN PLATEDKOVAR OR ALLOY42.
0.02 (0.508) 0.015 (0.381)
--H--
~~
=-tf
-.~ (4.45) 0.175
0.125 (3.18)
0.606 (15.4)
~",~" (0.203) I 0.008
0.105 (2.67)
0.58 (14.74) --J
28-PIN PLASTIC DIP (SUFFIX N)
IVVVVVVVVVVVVVVI 1.44 (36.581
1.45 (36.83)
OLE
811
0.55 (13.97)
-=r.47)
~ .
0.606(15.4)
rr
I
0.594 (15.091
~
~
\
-
0.16 (4.07) .14 (3.56)
TE
15.
8
o.,~
~
~~
0.065 11.661 0.045 (1.15)
~~
~~
0
~45)
0.02 (0.5081 0.105 (2.67) 0.12 (3.051 0.015 (0.3811 0.095 (2.42) NOTES, LEADNO.1 IS IDENTIFIEDBY DOTOR NOTCH. LEADSARE GOLD.PLATED(50 MICROINCHES MINI KOVAROR ALLOY42. CAVITYLID IS ELECTRICALL ISOLATED. Y
~ ::> z 0 w fZ a: a.
CJ:!
8
-12-

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